Specific Challenge:

High-resolution and high-speed data acquisition impose ever stronger real-time requirements on data processing components on which an increasing number of defence applications critically depend upon in areas such as communications, electronic warfare, encryption, digital imaging, as well as radar and secure positioning, navigation and timing (PNT). General purpose processors show too low performance levels for critical processes in such defence applications.

Hence the need for defence-specific hard- and software approaches. These functionalities can be embedded in high-density electronic components that can be configured or even reconfigured (such as Field Programmable Gate Arrays amongst others), are combined on a single System-on-Chip (SoC) or distributed over a Multi-Chip-Module (or other System-in-Package (SiP) solutions). The selection of the preferred technological solution should strike a balance between the requirements of the defence application(s) (in terms of, e.g., bandwidth, latency, flexibility, cryptologic restrictions, spatial requirements, power consumption), and economic drivers (such as the number of units expected to be produced, time to enter into service, the upfront costs (e.g., to non-recurring engineering), maintenance needs).

Performant (re)configurable SoC/SiPs are commercially available for a wide variety of applications in civil domains including medical and consumer electronics, automotive, and high performance computing. Using (re)configurable SoC/SiPs in (aero)space and defence applications adds stringent requirements for operation under harsh conditions. Moreover, military users need to be sure that these components can be trusted for use, e.g., in security systems, communication equipment and encryption algorithms available without restrictions.

For these technologies which are critical for a number of defence applications, the EU is currently fully dependent on suppliers established in non-EU countries, which implies risks of supply chains and vulnerabilities in terms of security. Furthermore, a number of regulations of non-EU nations can impose end-user restrictions on the use of the technologies (e.g., the US International Traffic in Arms and Export Administration Regulations (ITAR and EAR)). Setting up a EU-based supply chain for high-performance, trustable (re)configurable SoC/SiP for defence applications would contribute to remove these important limitations, as well as creating business opportunities in other highly demanding sectors beyond the defence sector.

Scope:

Proposals should design and validate a SoC/SiP and as such make a substantial contribution towards the development and manufacturing of European high-performance, trustable (re)configurable SoC/SiP suitable for multiple defence applications.

Design considerations and engineering decisions on the architecture of the SoC/SiP should thereby be driven by the state-of-the-art requirements of the selected defence applications. In particular long-term operation under harsh conditions, such as severe temperature variations, intense vibrations, and elevated radiation levels, as well as specific power requirements, should be adequately taken into account.

The design has to take into account that the manufacturing needs of the SoC/SiP should match the production capabilities of ideally more than one trustable fab or foundry established in the EU. In parallel to the proposed advances at the hardware level, advancing innovative development and debugging tools should be explored. They should enable to work at a high level of abstraction to design, simulate, integrate, synthesise, and test systems on the target device. Enhanced performance and shorter development times should be demonstrated by removing the debugging barrier between the processor and the (re)configurable component of the SoC/SiP.

Proposals should pay particular attention to security protection of the proposed hardware and software solutions.

The SoC/SiP architecture should be protected from intrusion or attacks, e.g., by secure boot mechanisms, embedding encryption engines, anti-tamper (which can be based on emerging technologies such as Physical Unclonable Functions (PUF)), anti-reverse engineering techniques and TEMPEST protection ideally allowing unclassified handling of information. The design and manufacturing process should be highly controlled to exclude that weaknesses, back doors or Trojan horses are implemented in the hardware and software components and systems. Flexible packaging options should be offered for the SoC/SiP device. When requested known good dies (KGD) should be supplied as well. The proposed security measures should be in line with the recommendations issued by the relevant national crypto approval authorities (CAA) of at least two Member States or Norway to handle information up to the national equivalents of SECRET UE/EU SECRET provided under Council Decision 2013/488/EU ^[3] and Commission Decision (EU, Euratom) 2015/444^[4].

Hardware and software products developed in the context of this topic should not be subject to non-EU export control regulations.

Proposals should include a size, weight, power and cost (SWaP-C) analysis to support the proposed (re)configurable SoC/SiP technology as well as a high-level description of the key performance indicators (KPIs) for state-of-the-art performance of the envisaged functionalities, and the methodologies on how to measure them. A report with a detailed description of these KPIs and methodologies should be delivered within 6 months after the start of the project.

In order to meet future capacity and performance requirements, the components should be implemented in a technology node (minimum transistor feature size) of 28 nm or smaller.

If the proposed architecture includes a FPGA, the SoC/SiP need to include at least the following features:

• 200k Look-Up Table (LUTs);
• Internal non-volatile memory;
• Digital Signal Processing hard-macros;
• Flexible interconnections between the DSP processing core, general processing cores and on- and off chip bridges and interfaces;
• Encryption module and anti-tamper and TEMPEST protection (as set out above);
• At least 10 Gb/s high-speed links / interfaces.

Deviations from the set of features listed above should be duly justified in view of the multiple defence applications envisaged.

The potential of the proposed solutions, in particular in the security and space domain^[5], should be thoroughly explored.

When relevant, results publicly available from EDA and NATO activities and studies should be taken into account for the proposed work. The activities included in the proposals should clearly differentiate from or go beyond work already covered under relevant themes of the EU Research and Innovation Framework Programmes.

The implementation of this topic is intended to start at TRL 2 to 3 and target TRL 5.

No more than one action will be funded.

Expected Impact:

• Convincing demonstration of the potential of EU-funded research in support of EU critical defence technologies, in particular in the domain of (re)configurable SoC/SiPs;
• Ensure secure and autonomous availability of high performance and trustable (re)configurable SoC/SiPs to military end-users;
• Contribute to strengthening the European microelectronics industry and help improve its global position through the implementation of innovative technologies along a new European manufacturing value chain;
• Improved competitiveness of the end-user industry in and beyond the defence sector.